APPENDIX AVI212 Spezifikationen PDF herunterladen (Seite 42)

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GAIA.ASU.SP.ESM.00007

Issue 2.00

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GAIA.ASU.SP.ESM.00007 (Avionics SCOE Req Iss 2).doc

3.6.7.1 FSS Simulation

AVI-750/GSE-SYS-404/T

For simulation of each FSS, the Avionics SCOE shall provide the following interfaces:

1 x Detector Voltage Simulation output (representing Q1 - Q4 or T1 - T4, as selected)

1 x 'Sun Presence' Voltage Simulation output (being the sum of Q1 - Q4)

Acquisition of 3 x EIU address line inputs (A0 - A2, for selection of the Detector Voltage Simulation output)

AVI-751/CREATED/T

Detector Voltage Simulation and 'Sun Presence' Voltage Simulation outputs shall conform to the

following specification: [AD06] Table 3.5-10 (Analog Driver Specification 2).

AVI-753/EIU-1173/T

EIU Address Line Acquisition shall conform to the following specification: CMOS Compatible, 0V -

12V nominal.

AVI-756/CREATED/T

Selection of the output voltage for Detector Voltage Simulation shall be determined by the EIU

Address Lines in accordance with the following truth table:

A0 A1 A2 Detector Voltage Simulation

0 0 0 Q1

0 0 1 Q2

0 1 0 Q3

0 1 1 Q4

1 0 0 T1

1 0 1 T2

1 1 0 T3

1 1 1 T4

Table 3.6-6: FSS - Address Line Truth Table Specification

Figure 3.6-4 shows typical timing of FSS Acquisition by the EIU:

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 78 79

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